1. Field of the Invention
The present invention relates to the technical field of adaptive decision feedback equalizer (ADFE) and, more particularly, to a fast convergent pipelined adaptive decision feedback equalizer (PADFE) using post-cursor processing filter (PCF), which is capable of eliminating the inter-symbol interference (ISI) in input samples.
2. Description of Related Art
Conventionally, the adaptive decision feedback equalizer (ADFE) using Least Mean-Squared (LMS) algorithm is one of the key technique in many magnetic storage and digital communication applications. FIG. 1 shows a block diagram of a serial adaptive decision feedback equalizer 100 (ADFE). As shown, in the serial ADFE 100, a feed-forward equalizer (FFE) 110 is provided for receiving the input samples x(n) and eliminating pre-cursor of the input samples x(n). An adder 150 adds the output signal of the FFE 110 and a feedback signal to produce an pre-quantization signal. A slicer 130 quantizes the pre-quantization signal and produces a white quantized signal. A register 140 is coupled to the slicer 130 for holding the white quantized signal. A feedback equalizer (FBE) 120 is provided for eliminating the post-cursor of the white quantized signal and producing the feedback signal. A subtractor 160 subtracts the pre-quantization signal from the quantized signal to produce a cost signal. An updating device 170 updates coefficients of the FFE 110 and FBE 120 based on the cost signal.
The updating mechanism of the serial ADFE 100 is based on the least mean square (LMS) error algorithm. The corresponding equations of the LMS-based serial ADFE 100 can be described as follows:
{tilde over (xcex1)}(n)=xcex1F(n)+xcex1B(n),xe2x80x83xe2x80x83(1a)
X(n)=[x(n) . . . x(nxe2x88x92Nf)],xe2x80x83xe2x80x83(1b)
Y(n)=[{circumflex over (xcex1)}(nxe2x88x921),{circumflex over (xcex1)}(nxe2x88x922), . . . {circumflex over (xcex1)}(nxe2x88x92Nb)],xe2x80x83xe2x80x83(1c)
xcex1F(n)=CT(nxe2x88x921)X(n),xe2x80x83xe2x80x83(1d)
xcex1B(n)=DT(nxe2x88x921)Y(n),xe2x80x83xe2x80x83(1e)
{circumflex over (xcex1)}(n)=Q[{circumflex over (xcex1)}(n)],xe2x80x83xe2x80x83(1f)
e(n)={circumflex over (xcex1)}(n)xe2x88x92{circumflex over (xcex1)}(n),xe2x80x83xe2x80x83(1g)
C(n)=C(nxe2x88x921)+xcexce(n)X(n),xe2x80x83xe2x80x83(1h)
D(n)=D(nxe2x88x921)+xcexce(n)Y(n),xe2x80x83xe2x80x83(1i)
where
xcex1F(n) is the output of FFE,
xcex1B(n) is the output of FBE,
C(n) is the vector of FFE coefficients,
D(n) is the vector of FBE coefficients,
X(n) is the vector of received samples,
Y(n) is the vector of detected symbols,
xc3xa3 (n) is the input of the slicer Q(xe2x80xa2),
xc3xa2 (n) is the output of the slicer Q(xe2x80xa2).
However, fine-grain pipelining of the serial ADFE 100 is known to be a difficult problem for high-speed applications and operating clock rate of the serial ADFE 100 is limited by a decision feedback loop (DFL) as shown in FIG. 1.
FIG. 2 shows a block diagram of a pipelined adaptive decision feedback equalizer 200 (PIPEADFE) for increasing the operating clock rate of the ADFE 100. To achieve the pipeline, a delay device 210 is introduced in the decision feedback loop. The delay device 210 is coupled between the register 140 and the feedback equalizer 120 for delaying the white quantized signal and increasing the number of pipeline stages for the feedback equalizer 120.
The equations for describing the pipeline adaptive decision feedback equalizer 200 (PIPEADFE) are summarized below:
{tilde over (xcex1)}(n)=xcex1F(n)+xcex1B(n),xe2x80x83xe2x80x83(2a)
X(n)=[x(n),x(nxe2x88x921), . . . x(nxe2x88x92Nf+1)],xe2x80x83xe2x80x83(2b)
Y(n)=[{circumflex over (xcex1)}(nxe2x88x921xe2x88x92D1),{circumflex over (xcex1)}(nxe2x88x921xe2x88x92D1), . . . {circumflex over (xcex1)}(nxe2x88x92D1xe2x88x92Nb)],xe2x80x83xe2x80x83(2c)
xcex1F(n)=CT(nxe2x88x92D4)X(n),xe2x80x83xe2x80x83(2d)
xcex1B(n)=DT(nxe2x88x92D4)Y(n),xe2x80x83xe2x80x83(2e)
{circumflex over (xcex1)}(n)=Q[{tilde over (xcex1)}(n)],xe2x80x83xe2x80x83(2f)
e(n)={circumflex over (xcex1)}(n)xe2x88x92{tilde over (xcex1)}(n),xe2x80x83xe2x80x83(2g)
                                          C            ⁡                          (              n              )                                =                                    C              ⁡                              (                                  n                  -                                      D                    4                                                  )                                      +                          μ              ⁢                                                ∑                                      i                    =                    0                                                        LA                    -                    1                                                  ⁢                                                      e                    ⁡                                          (                                              n                        -                                                  D                          2                                                -                        i                                            )                                                        ⁢                                      X                    ⁡                                          (                                              n                        -                                                  D                          2                                                -                        i                                            )                                                                                                          ,                            (                  2          ⁢          h                )                                                      D            ⁡                          (              n              )                                =                                    D              ⁡                              (                                  n                  -                                      D                    4                                                  )                                      +                          μ              ⁢                                                ∑                                      i                    =                    0                                                        LA                    -                    1                                                  ⁢                                                      e                    ⁡                                          (                                              n                        -                                                  D                          3                                                -                        i                                            )                                                        ⁢                                      Y                    ⁡                                          (                                              n                        -                                                  D                          3                                                -                        i                                            )                                                                                                          ,                            (                  2          ⁢          i                )            
The pipelined adaptive decision feedback equalizer (PIPEADFE) 200 maintains the functionality in the statistical behavior instead of input-output behavior by using the relaxed look-ahead technique. However, it suffers from some performance degradation such as output SNR and convergence rate. Although, the operating clock rate of the PIPEADFE 200 is large than the ADFE 100. But the convergence rate of PIPEADFE 200 is quite slower than the ADFE 100. Therefore, there is a need to have a novel design of pipeline adaptive decision feedback equalizer that can mitigate and/or obviate the aforementioned problems.
The object of the present invention is to provide a fast convergent pipelined adaptive decision feedback equalizer using a post-cursor processing filter for eliminating the inter-symbol interference (ISI) in input samples, so as to increase operating clock rate and convergence rate of overall system.
To achieve the aforementioned object, there is provided a fast convergent pipelined adaptive decision feedback equalizer using a post-cursor processing filter, which comprises a feed-forward equalizer, a post-cursor processing filter, an adder, a slicer, a register, a pipelined feedback equalizer, a subtractor and an updating device. The feed-forward equalizer is provided for receiving input samples and eliminating pre-cursor of the input samples. The post-cursor processing filter is coupled to the feed-forward equalizer for producing an output signal. The adder is provided for adding the output signal of the post-cursor processing filter and a feedback signal to produce an pre-quantization signal. The slicer is coupled to the adder for quantizing the pre-quantization signal and producing a white quantized signal. The register is coupled to the slicer for holding the white quantized signal. The pipelined feedback equalizer has plurality of pipeline stages and is coupled to the register for eliminating the post-cursor of the white quantized signal and producing the feedback signal. The subtractor is provided for subtracting the pre-quantization signal from the quantized signal to produce a cost signal. The updating device is provided for updating coefficients of the feed-forward equalizer and pipelined feedback equalizer based on the cost signal and updating coefficients of the post-cursor processing filter based on the cost signal and the white quantized signal.